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Magnify the Traditional Mixed-Signal Eyepatch Verification

Magnify the Traditional Mixed-Signal Eyepatch Verification

Weeks before tapeout, SoC design teams must verify large mixed-signal transistor-level netlists. The standard approach is to verify functionality by running simulations with back-annotated gate-level RTL along with behavioral analog blocks. However, since this...

French Tech Emergence status awarded to Aniah

French Tech Emergence status awarded to Aniah

In June 2020, the French Tech Emergence grant was awarded to Aniah. The French Tech Emergence grant is aimed at supporting Deeptech start-ups. BPI France evaluated Aniah's technology and value proposition and concluded that Aniah, as a company, has strong growth...

Electrical errors in ICs: why they occur and their consequences

Electrical errors in ICs:
why they occur and their consequences

The verification of electrical errors at chip-level has always been the missing step in chip design closure – even though a chip is, basically, a very large circuit. The complexity of such an analysis has so far made it impossible. Consequently, considerable effort is...