by Mexiiico | Oct 14, 2022 | stories
Aniah is proud to announce joining Cadence’s Connections Program earlier this year in May 2022. Our verification tool can now easily connect to Cadence Virtuoso Schematic Editor ®. From now on, our customers will be able to use Aniah ERC tool to check for errors...
by Mexiiico | Oct 14, 2022 | stories
This summer, our development team worked on the latest version of Aniah V2.1 ! It includes 4 brand-new features, for an easier use : – Synoptic schematic – Advanced-Power-Analysis – Verilog netlist support – Topology detection for a better...
by Mexiiico | Apr 8, 2022 | stories
The V2.0 has been released ! This release provides the full potential of electrical rules checking (ERC) while offering unprecedented ease of use. Its main assets are : – Comprehensive set of ERC rules natively supported. – Unparalleled performances and...
by Mexiiico | Apr 20, 2021 | stories
Weeks before tapeout, SoC design teams must verify large mixed-signal transistor-level netlists. The standard approach is to verify functionality by running simulations with back-annotated gate-level RTL along with behavioral analog blocks. However, since this...
by Mexiiico | Nov 23, 2020 | stories
In June 2020, the French Tech Emergence grant was awarded to Aniah. The French Tech Emergence grant is aimed at supporting Deeptech start-ups. BPI France evaluated Aniah’s technology and value proposition and concluded that Aniah, as a company, has strong growth...
