The V2.0 has been released ! This release provides the full potential of electrical rules checking (ERC) while offering unprecedented ease of use.
Its main assets are :
– Comprehensive set of ERC rules natively supported.
– Unparalleled performances and scalability.
– 100% coverage of powers scenarios.
– Fully integred, collaborative GUI.
– Dynamic error reporting.
Tested by our customers, our tool has demonstrated its ability to significantly increase design efficency.
Want to know more ? Contact us for a pratical demonstration
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Aniah joins Cadence Connections Programs
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Aniah Software V2.1
This summer, our development team worked on the latest version of Aniah V2.1 ! It includes 4 brand-new features, for an easier use : - Synoptic schematic - Advanced-Power-Analysis - Verilog netlist support - Topology detection for a better precision This new version...
Magnify the Traditional Mixed-Signal Eyepatch Verification
Weeks before tapeout, SoC design teams must verify large mixed-signal transistor-level netlists. The standard approach is to verify functionality by running simulations with back-annotated gate-level RTL along with behavioral analog blocks. However, since this...
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