Weeks before tapeout, SoC design teams must verify large mixed-signal transistor-level netlists. The standard approach is to verify functionality by running simulations with back-annotated gate-level RTL along with behavioral analog blocks. However, since this approach might overlook serious errors, old-fashion eyeball checking remains necessary.
This whitepaper exhibits some situations that might get overlooked by the standard approach and eyeball checking. There is also a description of the difficulties of performing mixed-signal tests that could detect these types of situations. To overcome this verification challenge, we introduce a reliable static electrical analysis tool that runs built-in assertion checks to netlists with billions of devices in a short runtime.
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Aniah Software V2.0 Deployment
The V2.0 as been released ! This release provides the full potential of electrical rules checking (ERC) while offering unprecedented ease of use. Its main assets are : - Comprehensive set of ERC rules natively supported. - Unparalleled performances and scalability. -...
French Tech Emergence status awarded to Aniah
In June 2020, the French Tech Emergence grant was awarded to Aniah. The French Tech Emergence grant is aimed at supporting Deeptech start-ups. BPI France evaluated Aniah's technology and value proposition and concluded that Aniah, as a company, has strong growth...
ERC: a trade-off between coverage and false positives?
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