Weeks before tapeout, SoC design teams must verify large mixed-signal transistor-level netlists. The standard approach is to verify functionality by running simulations with back-annotated gate-level RTL along with behavioral analog blocks. However, since this approach might overlook serious errors, old-fashion eyeball checking remains necessary.
This whitepaper exhibits some situations that might get overlooked by the standard approach and eyeball checking. There is also a description of the difficulties of performing mixed-signal tests that could detect these types of situations. To overcome this verification challenge, we introduce a reliable static electrical analysis tool that runs built-in assertion checks to netlists with billions of devices in a short runtime.
Other stories
Aniah joins Cadence Connections Programs
Aniah is proud to announce joining Cadence's Connections Program earlier this year in May 2022. Our verification tool can now easily connect to Cadence Virtuoso Schematic Editor ®. From now on, our customers will be able to use Aniah ERC tool to check for errors and...
Aniah Software V2.1
This summer, our development team team worked on the latest version of Aniah V2.1 ! It includes 4 brand-new features, for an easier use :- Synoptic schematic- Advanced-Power-Analysis- Verilog netlist support- Topology detection for a better precision This new version...
Aniah Software V2.0 Deployment
The V2.0 as been released ! This release provides the full potential of electrical rules checking (ERC) while offering unprecedented ease of use. Its main assets are : - Comprehensive set of ERC rules natively supported. - Unparalleled performances and scalability. -...
Stay Tuned
Sign up for our newsletter to receive
aniah’s latest development and release