The verification of electrical errors at chip-level has always been the missing step in chip design closure – even though a chip is, basically, a very large circuit. The complexity of such an analysis has so far made it impossible.
Consequently, considerable effort is made throughout the design flows to avoid electrical errors from occurring in the first place. Experience, however, shows that without a verification solution dedicated to the analysis of electrical circuits at the chip scale, some errors elude the vigilance of design engineers, even with the most comprehensive design flows.
Those errors have severe consequences, ranging from delays in the project schedule (thus increasing its cost), failed time-to-market and in the worst case, product recalls (and the major financial as well as brand image impacts this can imply).
In this document, we go over why chips routinely go to fab with undetected electrical errors and the consequences that such errors have on a chip project success and lifetime.
Aniah is proud to announce joining Cadence's Connections Program earlier this year in May 2022. Our verification tool can now easily connect to Cadence Virtuoso Schematic Editor ®. From now on, our customers will be able to use Aniah ERC tool to check for errors and...
This summer, our development team worked on the latest version of Aniah V2.1 ! It includes 4 brand-new features, for an easier use : - Synoptic schematic - Advanced-Power-Analysis - Verilog netlist support - Topology detection for a better precision This new version...
The V2.0 has been released ! This release provides the full potential of electrical rules checking (ERC) while offering unprecedented ease of use. Its main assets are : - Comprehensive set of ERC rules natively supported. - Unparalleled performances and scalability. -...
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