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A revolutionary IC verification tool to

Quickly and easily clean all electrical errors on all chip designs

Why is full-chip electrical verification essential?

Semiconductor manufacturers suffer from electrical errors in their designs that cannot be detected.

Integrated Circuits routinely go to fab with dozens of electrical errors due to the lack of a dedicated verification solution.

Existing EDA solutions are either accurate but limited in capacity or, due to oversimplification, unable to identify all errors.

Design best-practices reduce the problem, but cannot solve it completely.

The financial impact of these errors can reach hundreds of millions of dollars in the event of a product recall.

Beyond the financial impact, it can also seriously damage a company’s image.

What makes Aniah different?


100% exhaustive and accurate

Detects all errors thanks to an electrically-accurate analysis at transistor-level on the full IC.

Built from the ground up to remove the burden of false errors

Covers all possible power states in a single run

Enables focusing on correcting real errors rather than filtering out false errors


Easy to use for all IC designers

Minimizes setup effort thanks to Aniah’s “analysis first” approach

Reports errors in an understandable manner

Provides the benefits of formal verification at transistor level to analog and digital design engineers

Allows full customization with no impact on tool performance

Very easy to use for all IC design engineers
From 100s to 2000s of times shorter


100 times faster full-chip analysis

Introduces a new performance class for an electrically accurate analysis

Reports errors in their relevant context for immediate review and correction

Provides relevant results within seconds to continuously improve designs and reduce time to sign off


Great performances from small to tera-transistor circuits

Built from the ground up to leverage the latest advances in computer science technologies​

Designed for large-scale parallelization on hundreds of cores​

Analyzes chips with billions of transistors in a few minutes, limiting the impact on the project and the sign-off schedule​

Too good to be true?
Contact us and ask for a demo on your design

Our stories

Aniah joins Cadence Connections Programs

Aniah joins Cadence Connections Programs

Aniah is proud to announce joining Cadence's Connections Program earlier this year in May 2022. Our verification tool can now easily connect to Cadence Virtuoso Schematic Editor ®. From now on, our customers will be able to use Aniah ERC tool to check for errors and...

Aniah Software V2.1

Aniah Software V2.1

This summer, our development team worked on the latest version of Aniah V2.1 ! It includes 4 brand-new features, for an easier use : - Synoptic schematic - Advanced-Power-Analysis - Verilog netlist support - Topology detection for a better precision This new version...

Aniah Software V2.0 Deployment

Aniah Software V2.0 Deployment

The V2.0 has been released ! This release provides the full potential of electrical rules checking (ERC) while offering unprecedented ease of use. Its main assets are : - Comprehensive set of ERC rules natively supported. - Unparalleled performances and scalability. -...

Our team

Vincent Bligny

Vincent Bligny

CEO & Founder

Vincent spent a decade solving the problem of electrical errors and improving productivity in circuit design. His understanding of EDA issues forms the basis of Aniah’s strategy.
Rémi Moriceau

Rémi Moriceau

CTO & Founder

Rémi trains and leads Aniah’s technical teams in a continuous quality testing process to offer the most advanced EDA solutions tailored to the needs of our customers.
  • Founded in

    2019, Q4

  • Funding


    Q4 2021

  • Team of

    14 people

    (inc. 11 R&D engineers)

  • 1st Product available

    2020, Q4

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