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A revolutionary IC verification tool to

Quickly and easily clean all electrical errors on all chip designs

Why is full-chip electrical verification essential?

Semiconductor manufacturers suffer from electrical errors in their designs that cannot be detected.

Integrated Circuits routinely go to fab with dozens of electrical errors due to the lack of a dedicated verification solution.

Existing EDA solutions are either accurate but limited in capacity or, due to oversimplification, unable to identify all errors.

Design best-practices reduce the problem, but cannot solve it completely.

The financial impact of these errors can reach hundreds of millions of dollars in the event of a product recall.

Beyond the financial impact, it can also seriously damage a company’s image.

What makes Aniah different?

RELIABLE

100% exhaustive and accurate

Detects all errors thanks to an electrically-accurate analysis at transistor-level on the full IC.

Built from the ground up to remove the burden of false errors

Covers all possible power states in a single run

Enables focusing on correcting real errors rather than filtering out false errors

INTUITIVE

Easy to use for all IC designers

Minimizes setup effort thanks to Aniah’s “analysis first” approach

Reports errors in an understandable manner

Provides the benefits of formal verification at transistor level to analog and digital design engineers

Allows full customization with no impact on tool performance

Very easy to use for all IC design engineers
From 100s to 2000s of times shorter

FAST

100 times faster full-chip analysis

Introduces a new performance class for an electrically accurate analysis

Reports errors in their relevant context for immediate review and correction

Provides relevant results within seconds to continuously improve designs and reduce time to sign off

SCALABLE

Great performances from small to tera-transistor circuits

Built from the ground up to leverage the latest advances in computer science technologies​

Designed for large-scale parallelization on hundreds of cores​

Analyzes chips with billions of transistors in a few minutes, limiting the impact on the project and the sign-off schedule​

Too good to be true?
Contact us and ask for a demo on your design

Our stories

Aniah Software V2.0 Deployment

Aniah Software V2.0 Deployment

The V2.0 as been released ! This release provides the full potential of electrical rules checking (ERC) while offering unprecedented ease of use. Its main assets are : - Comprehensive set of ERC rules natively supported. - Unparalleled performances and scalability. -...

Magnify the Traditional Mixed-Signal Eyepatch Verification

Magnify the Traditional Mixed-Signal Eyepatch Verification

Weeks before tapeout, SoC design teams must verify large mixed-signal transistor-level netlists. The standard approach is to verify functionality by running simulations with back-annotated gate-level RTL along with behavioral analog blocks. However, since this...

French Tech Emergence status awarded to Aniah

French Tech Emergence status awarded to Aniah

In June 2020, the French Tech Emergence grant was awarded to Aniah. The French Tech Emergence grant is aimed at supporting Deeptech start-ups. BPI France evaluated Aniah's technology and value proposition and concluded that Aniah, as a company, has strong growth...

Our team

Vincent Bligny

Vincent Bligny

CEO & Founder

Vincent spent a decade solving the problem of electrical errors and improving productivity in circuit design. His understanding of EDA issues forms the basis of Aniah’s strategy.
Rémi Moriceau

Rémi Moriceau

CTO & Founder

Rémi trains and leads Aniah’s technical teams in a continuous quality testing process to offer the most advanced EDA solutions tailored to the needs of our customers.
François Vieillard

François Vieillard

Business Development

François’ creative and agile approach while considering the industrial ecosystem, allows him to initiate and structure the best partnerships with our customers.
  • Founded in

    2019, Q4

  • Funding

    2,3m€

    Q4 2021

  • Team of

    14 people

    (inc. 11 R&D engineers)

  • 1st Product available

    2020, Q4

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LOCATED IN GRENOBLE,

France

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