A revolutionary IC verification tool to
Quickly and easily clean all electrical errors on all chip designs
Why is full-chip electrical verification essential?
Semiconductor manufacturers suffer from electrical errors in their designs that cannot be detected.
Integrated Circuits routinely go to fab with dozens of electrical errors due to the lack of a dedicated verification solution.
Existing EDA solutions are either accurate but limited in capacity or, due to oversimplification, unable to identify all errors.
Design best-practices reduce the problem, but cannot solve it completely.
The financial impact of these errors can reach hundreds of millions of dollars in the event of a product recall.
Beyond the financial impact, it can also seriously damage a company’s image.
What makes Aniah different?
100% exhaustive and accurate
Detects all errors thanks to an electrically-accurate analysis at transistor-level on the full IC.
Built from the ground up to remove the burden of false errors
Covers all possible power states in a single run
Enables focusing on correcting real errors rather than filtering out false errors
Easy to use for all IC designers
Minimizes setup effort thanks to Aniah’s “analysis first” approach
Reports errors in an understandable manner
Provides the benefits of formal verification at transistor level to analog and digital design engineers
Allows full customization with no impact on tool performance
100 times faster full-chip analysis
Introduces a new performance class for an electrically accurate analysis
Reports errors in their relevant context for immediate review and correction
Provides relevant results within seconds to continuously improve designs and reduce time to sign off
Great performances from small to tera-transistor circuits
Built from the ground up to leverage the latest advances in computer science technologies
Designed for large-scale parallelization on hundreds of cores
Analyzes chips with billions of transistors in a few minutes, limiting the impact on the project and the sign-off schedule
Too good to be true?
Contact us and ask for a demo on your design
Weeks before tapeout, SoC design teams must verify large mixed-signal transistor-level netlists. The standard approach is to verify functionality by running simulations with back-annotated gate-level RTL along with behavioral analog blocks. However, since this...
In June 2020, the French Tech Emergence grant was awarded to Aniah. The French Tech Emergence grant is aimed at supporting Deeptech start-ups. BPI France evaluated Aniah's technology and value proposition and concluded that Aniah, as a company, has strong growth...
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CTO & Founder
Software Architect & Founder
CFO & Founder
Marketing & Sales
Business Development Director
(inc. 11 R&D engineers)
1st Product available
LOCATED IN GRENOBLE,
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