A revolutionary IC verification tool to
Quickly and easily clean all electrical errors on all chip designs
Why is full-chip electrical verification essential?
Semiconductor manufacturers suffer from electrical errors in their designs that cannot be detected.
Integrated Circuits routinely go to fab with dozens of electrical errors due to the lack of a dedicated verification solution.
Existing EDA solutions are either accurate but limited in capacity or, due to oversimplification, unable to identify all errors.
Design best-practices reduce the problem, but cannot solve it completely.
The financial impact of these errors can reach hundreds of millions of dollars in the event of a product recall.
Beyond the financial impact, it can also seriously damage a company’s image.
What makes Aniah different?
RELIABLE
100% exhaustive and accurate
Detects all errors thanks to an electrically-accurate analysis at transistor-level on the full IC.
Built from the ground up to remove the burden of false errors
Covers all possible power states in a single run
Enables focusing on correcting real errors rather than filtering out false errors
INTUITIVE
Easy to use for all IC designers
Minimizes setup effort thanks to Aniah’s “analysis first” approach
Reports errors in an understandable manner
Provides the benefits of formal verification at transistor level to analog and digital design engineers
Allows full customization with no impact on tool performance
FAST
100 times faster full-chip analysis
Introduces a new performance class for an electrically accurate analysis
Reports errors in their relevant context for immediate review and correction
Increases the speed and reliability of the verification process by allowing design updates to be confirmed within seconds
SCALABLE
Ready for tera-transistors SoC
Built from the ground up to leverage the latest advances in computer science technologies
Designed for large-scale parallelization on hundreds of cores
Analyzes chips with billions of transistors in a few minutes, limiting the impact on the project and the sign-off schedule
Too good to be true?
Contact us and ask for a demo on your design
Our stories
French Tech Emergence status awarded to Aniah
In June 2020, the French Tech Emergence grant was awarded to Aniah. The French Tech Emergence grant is aimed at supporting Deeptech start-ups. BPI France evaluated Aniah's technology and value proposition and concluded that Aniah, as a company, has strong growth...
ERC: a trade-off between coverage and false positives?
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Electrical errors in ICs:
why they occur and their consequences
The verification of electrical errors at chip-level has always been the missing step in chip design closure – even though a chip is, basically, a very large circuit. The complexity of such an analysis has so far made it impossible. Consequently, considerable effort is...
Our founder’s motivations
Vincent Bligny
CEO
Rémi Moriceau
CTO
Benoit Lemaignan
CFO
- Electrical errors have plagued IC projects for too long: I founded Aniah to finally solve this issue.
- I wasn’t aware that it was impossible to do formally a full topology coverage at lightning speed, so I made it
- Supporting the development of such a disruptive approach to improve industrial efficiency was a no-brainer
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Founded in
2019, Q4
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Funding
1,1m€
Q2 2020
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Team of
8 people
(inc. 6 R&D engineers)
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1st prototype success
2020, Q2
Awarded
Emergence status
DeepTech startups fast-track program
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